Title |
Library Technologies, Inc. |
Description |
Library Technologies, Inc. |
Keywords |
ASIC,
automatic characterization,
block characterization,
cadence,
cell characterization,
cell library characterization,
circuit delay optimization,
circuit modeling,
circuit optimization,
circuit power optimization,
circuit simulation,
critical path optimization,
clock skew,
clock tree,
clock tree synthesis,
clock network,
clock latency,
clock grid,
cool chips,
deep sub-micron,
delay calculation,
design automation,
design reuse,
device sizing,
electrical DFY,
electrical DFM,
EDA,
ground bounce,
intellectual property,
interconnect,
IR drop,
IP characterization,
IP Modeling,
extraction,
layout synthesis,
libchar,
library development,
Library Generator,
library technologies,
liberty format,
liberty library,
memory characterization,
memory modeling,
monte carlo analysis,
statistical static timing analysis,
static timing analysis,
statistical variation,
transistor-level statistical variation,
process variation,
yield optimization,
SSTA |
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